In many electronic applications, a measure of analog single-ended low frequency signals is often required. Usually, a General-Purpose Analog-to-Digital Converter or GPADC is used to convert such analog signals from the analog domain to the digital domain while measuring them. One of these electronic applications is, for example, mobile phones wherein many analog signals have to be continuously monitored to keep the microprocessor equipping each mobile phone device aware of the state of the device itself.
According to the analog-to-digital conversion procedure, an analog signal to be converted, for example a voltage signal having a respective range of variation, is compared to a reference range often indicated as Full Scale Range or FSR. Usually, a single FSR is provided whereas different signals to be converted can have each a different range. In view of this, scaling voltage signals before starting the analog-to-digital conversion is a common practice in order to align the ranges of such voltage signals to the reference range. Moreover, most of the voltage signals to be converted are single-ended signals and referred to ground, whereas few voltage signals have their respective ranges shifted with respect to the ground reference. Therefore, for such few voltage signals also a shifting of the voltage signal's range is required.
An example of a shifted voltage signal is the battery voltage in mobile phones. The analog-to-digital conversion of the battery voltage is always required in such devices. For example, the battery voltage range having a minimum value of 2.3V (battery low) and a maximum value of 4.8V (battery charged) is usually converted using a reference FSR=1.6V. In this case, the battery range is 4.8V−2.3V=2.5V and such range is scaled into 1.6V range by applying 1.6V/2.5V=0.64 as a scaling factor. After the scaling process, the resulting range is:Vmin=(2.3V*0.64)=1.472VVmax=(4.8V*0.64)=3.072V.
Furthermore, a voltage shifting is required as indicated above. This is obtained by subtracting the minimum scaled voltage Vmin to both voltages resulting from the scaling process, so that:Vmin1=(1.472V−1.472V)=0V; Vmax1=(3.072V−1.472V)=1.6V.
It should be observed that whereas a voltage scaling can be implemented with an electronic circuit without efforts, voltage shifting is much more complicated to be circuitally implemented.
A well-known solution in the art to convert a analog battery voltage into a digital domain is based on charge redistribution provided by a GPADC device operating with a Successive Approximation Register or SAR. A General-Purpose ADC SAR device is disclosed, for example, in document US 2003/0231130 A1.
FIG. 3 of the present application shows an exemplary structure of a GPADC SAR device 500 known in the art.
The GPADC SAR device 500 comprises a comparator 501 having a first input A connected to a capacitive DAC array 502 for providing a voltage representing the difference between a sampled input voltage VM, applied to a first input terminal 1 of the device 500, and a fraction of a reference voltage VREF, applied to a second input terminal 2 of the same device. Such fraction is obtained by connecting only a portion of the capacitors of the array 502 to the reference voltage VREF. This operation is managed by a SAR algorithm controller. A second input B of the comparator 501 and a third input terminal 12 of the GPADC device 500 are both connected to the ground potential GND. The input voltage signal VM of the GPADC SAR device 500 is sampled and stored on the DAC capacitive array 502. This solution is both simple and has the advantage to allow the scaling down of the input voltage VM stored in the DAC 502 to a voltage equal to the reference voltage VREF only by charging a prefixed fraction of capacitors comprised in the DAC array 502.
In the GPADC SAR device 500, the voltage shifting is achieved by adding a further capacitor, particularly capacitor CAUX in FIG. 3, to the summing node of the capacitive array 502 corresponding to the first input A of comparator 501. In the case of a battery voltage shifting, the additional capacitor CAUX is substantially as big as the whole capacitive array 502. For example, assuming the input voltage signal VM in the range (2.3V-4.8V), a value for the additional capacitor CAUX is obtained by the equation:
                              C          AUX                =                                            C              array                        ·                                          2.3                ⁢                                                                  ⁢                V                                                              (                                      4.8                    -                    2.3                                    )                                ⁢                V                                              =                      0.92            ·                          C              array                                                          (                  1          ′                )            wherein Carray corresponds substantially to the total capacitance of the capacitive array 502. Therefore, the resulting area occupation of such array 502 is roughly doubled.
Moreover, the total capacitances connected to the first A input of comparator 501 increases the voltage attenuation of both the input voltage signal VM and the comparison voltage generated by the SAR algorithm. Therefore, the signal to noise ratio S/N at the input of the comparator 501 is significantly worsened. Such disadvantage of the GPADC SAR device 500 is particularly relevant in new technologies wherein supply voltages are gradually reduced.
The GPADC SAR device 500 has further disadvantages. In fact, since the input voltage signal VM to be converted can reach a value up to 4.8V (corresponding to the fully charged battery), a voltage of the same value has to be made available inside the GPADC SAR device 500. In recent technologies, for example for a 40 nm manufacturing process or subsequent, reliability issues appear if the voltage inside the circuit overcome very limited values as 3.3V or even 2.5V: so many modifications have to be introduced to manage such a battery voltage value inside the device 500 which lead to area and complexity increases as well as growth in power consumption.
In an alternative solution described with reference to FIG. 4, a resistive voltage divider 600 can be provided at the input of the GPADC SAR device 500. Particularly, such voltage divider 600 comprises resistors RA, RB to scale the input voltage VM in order to generate a properly scaled voltage VM′ at the input of the GPADC SAR device 500. However, the voltage shifting is still performed inside the GPADC SAR 500 by using the above mentioned additional capacitor CAUX.
Such alternative solution ensures a complexity reduction of the GPADC SAR device 500 compared with the previous one and, therefore, is more reliable. However, with reference to the chip area occupation involved, even if the additional area occupied by the resistive voltage divider would probably compensate for the area saved inside the GPADC SAR device 500 determined by reliability drawbacks prevention, the area required for voltage shifting, which is influenced by capacitor CAUX, is not reduced at all. Therefore, also such alternative solution suffers of a non negligible increase in area occupation.